This invention relates to programmable logic integrated circuit devices, and more particularly to the signal routing resources in such devices.
Programmable logic integrated circuit devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611, both of which are hereby incorporated by reference herein. Such devices typically include a large number of regions of programmable logic. Each logic region is programmable to produce an output signal which is any one of a number of relatively elementary logic functions of several input signals applied to the logic region. The logic regions are typically disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection conductors are provided along the rows and columns for conveying signals to, from, and between the logic regions. For example, horizontal conductors may be associated with each row of regions for conveying signals along the associated row. Vertical conductors may be associated with each column of regions for conveying signals along the associated column. Programmable logic connectors ("PLCs") are provided for programmably connecting (1) selected adjacent interconnection conductors to the inputs of each logic region, (2) the output of each logic region to selected interconnection conductors adjacent to the logic region, and (3) selected interconnection conductors to one another (e.g., connecting selected horizontal conductors to selected vertical conductors). In this way any number of the logic regions can be concatenated to perform very complex logic functions.
Because of the large number of logic regions provided in a typical programmable logic device, it is not practical or economical to provide completely universal interconnection conductor resources on the device. Such universal resources would allow any interconnection to be made to, from, or between logic regions regardless of what other interconnections had been made. An excessive fraction of the overall resources of the device would have to be devoted to interconnection resources if such complete universality were provided, and large amounts of such universal resources would be unused in most (if not substantially all) cases. It is therefore important to devise less than completely general interconnection structures that are highly efficient (in the sense that they take up a significantly-reduced fraction of the overall resources of the device) but still afford a high degree of interconnectivity and signal routing flexibility. Because programmable logic devices are general-purpose devices, it is desirable to construct them so that they have the widest possible applicability (consistent with other objectives such as desired size, speed, power consumption, cost, etc.). Efficient interconnection structures are very important to achieving all of these objectives.
Among the important components of typical programmable logic device interconnection structures are driver circuits. Such driver circuits may be used to apply the output signal of each logic region to the horizontal and/or vertical interconnection conductors associated with that region. A driver circuit is needed to make sure that the logic region output signal is strong enough to drive the conductor to which it is applied, as well as the further circuitry that receives the signal from that conductor. The necessary driver circuits therefore tend to be relatively large and power-consuming. They may also need to be programmable and/or tri-statable, and to therefore be accompanied by auxiliary circuitry such as programmable memory cells. It is accordingly desirable to try to reduce the required number of driver circuits and/or to make better use of the driver circuits that are provided.
In view of the foregoing, it is an object of this invention to provide improved programmable logic devices.
It is a more particular object of this invention to provide improved interconnection resource structures for programmable logic devices.
It is a still more particular object of this invention to make better use of the driver circuits that are provided in the interconnection resources of programmable logic circuits, possibly allowing the number of such circuits to be reduced without sacrificing signal routing flexibility and/or allowing increased signal routing flexibility with a given number of driver circuits.